The present invention relates to a semiconductor chip, a semiconductor device having a structure in which semiconductor chips are stacked, and a method of measuring a semiconductor device.
Recently, proposals have been made about a semiconductor device which has a multilayer structure of stacking semiconductor chips through a number of through electrodes, which are called through silicon vias (TSVs). In a semiconductor device having such a multilayer structure, a continuity test or conduction test is performed for each of TSVs after the stacking of semiconductor chips in order to determine whether or not a normal connection is established between the semiconductor chips. In this case, a continuity test is usually conducted for each of TSVs by bringing a test terminal into contact with a signal bump provided on each of the TSVs. However, since a great number of TSVs are provided in such a semiconductor device, a huge amount of man-hours are required for continuity tests if a continuity test is performed for every one of the TSVs.
In a case where a continuity test of a TSV is usually carried out after a semiconductor device has been assembled into a product, the entire product becomes defective if any defect is found between TSVs after the assembly.
Meanwhile, JR-A 2009-139273 (Patent Literature 1) discloses a multilayer semiconductor device and a continuity test method that can individually confirm a connection state of each of semiconductor chips of a semiconductor device. In order to confirm a connection state of each layer of the semiconductor chips after stacking of the semiconductor chips, a test-dedicated terminal is provided on each of the semiconductor chips, and a diode for a continuity test is connected between the test-dedicated terminal and an internal terminal.
JP-A 2011-145257 (Patent Literature 2) discloses a semiconductor device having an interface chip and a core chip separated from each other. The interface chip and the core chip are electrically coupled to each other by a measurement signal wiring including a through electrode and a reference signal wiring. Specifically, Patent Literature 2 proposes providing a signal generation circuit and a signal judgment circuit on the interface chip, transmitting a test clock and a predetermined measurement signal to the core chip from the signal generation circuit, and detecting a phase difference of the predetermined measurement signals received via the measurement signal wiring and the reference signal wiring.
Both of Patent Literature 1 and Patent Literature 2 propose a test method of a semiconductor device having semiconductor chips with through electrodes after the semiconductor device has been assembled into a product. Furthermore, a connection state is confirmed by electrically coupling signal through electrodes and confirming a connection state of signal wirings between the semiconductor chips.
According to inventors' study, it has been found that, if a connection failure or defect occurs between semiconductor chips, the connection failure widely extends not only to signal through electrodes, but also to the vicinity of the signal through electrodes. If such a connection failure or defect can be detected at an early stage, a semiconductor chip can be restacked, so that a remarkable increase of yields of products can be expected.